1. Field of the Invention
The present invention relates to a memory, such as DRAM (dynamic RAM), whose power consumption for refresh is reduced to such a level as that of medium and low speed devices, such as SRAM (static RAM), in its data retention mode.
2. Background of the Invention
Certain memory devices, such as SRAM""s, are able to hold data with low power so that it has various uses for low power applications such as when batteries are used as a power supply. However, SRAM""s for low power applications have a large cell area because they are comprised of six transistors per cell, therefore, they are not suitable for memory with a large capacity. In particular, comparing a DRAM cell according to the recent technology, an area of an SRAM cell is eight to twelve times greater than that of DRAM when using the same design rule. Utilizing superiority of the area efficiency of DRAM, there is a trend toward replacing low-power SRAM with DRAM in the situation where the capacity is too large for SRAM but too small for DRAM.
A problem when replacing an SRAM with DRAM is that refresh is unnecessary for SRAM but necessary for DRAM. In particular, in order to hold data even when the memory chip is in the standby state, a typical DRAM consumes several milliamperes of current, which is about 100 times that of SRAM. Therefore, it is difficult to replace an SRAM with DRAM as it is. A method for reducing this current consumption for holding data may include increasing a retention time for DRAM cells by improving the process technology or selecting chips that have a long retention time by screening.
However, in order to reduce current consumption of DRAM for holding data to about one hundredth being similar to that of SRAM, the retention time must be increased one hundred times, which is practically impossible. Therefore, replacing an SRAM capable of holding data with a low power DRAM has not been implemented to date. The reason for this will be described in detail below.
First, refresh current components will be analyzed. Though refresh is the same as normal row accesses, it needs no column address. As such, the operation is completed within a cycle of about 100 ns identical to normal accesses, during which current consumption is smaller than the normal row accesses because no column access exists, but still several tens of milliamperes are consumed. Since refresh normally occurs once for 16 Âxcexcs, an average refresh current is a small value of several milliamperes, which is equal to the product of row access current and a ratio of row access cycle time to a refresh period.
Row access current, which consists of array and peripheral components, will be analyzed further. First, in the memory array, current flows because a number of bit line pairs are driven by sense amplifiers, wherein for each bit line pair, one bit line rises from the precharged voltage to an array power supply voltage, which is equal to half of the array power supply voltage, while the other falls from the precharged voltage to the ground. The refresh current, la ref, for the memory array caused by this operation is given by the following equation.                                           Equation            ⁢                          xe2x80x83                        ⁢            1                    :                      
                    ⁢          Iaref                =                              Na            xc3x97            Cb            xc3x97            Vsw                    Tcref                                    (        1        )            
where, Na is the number of sense amplifiers activated by one row access, Cb is capacitance of one bit line, Vsw is a voltage swing of the bit line driven by the sense amplifier, and Tcref is a refresh period.
Furthermore, assuming that Nm is the total number of memory cells in the chip, Nw is the number of word lines to be refreshed repetitively, and Tret is a retention time of the cell, Nm and Tret are given as follows, respectively.
Equation 2:
Nm=Naxc3x97Nwxe2x80x83xe2x80x83(2)
Equation 3:
Tret=Tcrefxc3x97Nwxe2x80x83xe2x80x83(3)
Thus, substituting Equations 2 and 3 for Equation 1, the following is obtained.                                           Equation            ⁢                          xe2x80x83                        ⁢            4                    :                      
                    ⁢          Iaref                =                              Cb            xc3x97            Vsw            xc3x97            Nm                    Tret                                    (        4        )            
Equation 4 shows that for a memory having a predetermined number of bits, the current for the array portion is constant if the retention time of the cell is given. Namely, the refresh current remains the same regardless of refresh modes; a longer refresh period with many cells refreshed at a time or a shorter period with smaller cells. Moreover, Equation 4 shows that the refresh current decreases as the retention time is increased, however, it is impossible to increase the retention time such as 100 times or so.
On the other hand, the retention current for the peripheral circuits would be the product of the ratio of row access cycle time to a refresh cycle time and the operation current at row accesses, when it is assumed that the retention current consists of AC current only. Therefore, as the refresh period increases, this current decreases. As a whole, it is summarized that the refresh current for the array portion is constant while the refresh current for the peripheral circuits decreases if the number of cells to be refreshed at a time increases. Thus, the total refresh current decreases when refresh period becomes longer.
Table 1 shows calculated refresh currents for the above discussion for a 16 Mb DRAM assuming a 0.18 Âxcexcm DRAM technology.
Table 1 assumes that operation current is 10.5 mA when row accesses are performed in 80 ns cycle time, wherein 0.5 mA is consumed in the array portion and 10 mA is consumed in the peripheral circuits when a small number, 256, of sense amplifiers are activated (i.e., page length is 256 bits). The refresh current for the array portion is given by the above Equation 4. For a 16 Mb memory with 64 ms retention time, the refresh current is 37 ÂxcexcA according to Equation 4 assuming that the bit line capacitance is 0.14 pF when 512 word lines exist per bit line and the bit line voltage swing is 1 V.
By increasing Na, the number of sense amplifiers to be activated at a time, from 256 to 32K, Nw, the number of word lines to be activated, which is necessary to complete refresh for a 16 Mb entire chip, decreases, and the refresh period Tcref increases, as shown in Table 1. For the same retention time such as 64 ms, as the number of sense amplifiers increases, the refresh current for the array portion remains the same 37 ÂxcexcA. However, the refresh current for the peripheral circuits decreases, consequently the total retention current decreases from 856 ÂxcexcA for 256 sense amplifiers to 73 ÂxcexcA for 8K sense amplifiers.
However, since the retention current decreases down only to one tenth, the retention time must be increased to decrease the retention current much more, as shown in Table 1. However, it is practically impossible to increase the retention time as described above.
Therefore, for a given capacity of memory (i.e., Nm is fixed) even with the conventional 64 ms retention time, a new method for more than ten-times reduction in refresh current is required. Equation 4 shows that the refresh current can be reduced by decreasing the bit line capacitance and bit line voltage swing when Nm and Tret are given.
In order to decrease the bit line capacitance, its length may be shortened from a typical structure having 512 word lines to the one that has 256, 128 or 64 word lines.
As the length of bit lines decreases, the capacitance of them also decreases, thus a read signal would advantageously grow. In order to utilize the large read signal, it is conceivable to increase the retention time. This allows moving a center of the distribution of retention time to a longer value, however, what actually determines the retention time is the foot of the distribution in the shorter range that is dependent on defects or the like, so that this range can not be improved even by increasing the read signal. As a result, the increase in retention time is impossible.
It is therefore an object of the present invention to provide a method for reducing DRAM refresh current in both components of the memory array and peripheral circuits.
Another object of the present invention is to reduce data retention current for refresh for DRAM to about one hundredth of the prior current in order to replace an SRAM with DRAM. Thus, it aims to reduce memory cost significantly by exploiting DRAM""s advantage in density.
According to the present invention, there is provided a DRAM having multiple blocks composing an array, wherein in each block a predetermined number of word lines and a predetermined number of bit lines are arranged in a matrix form and a sense amplifier is provided, wherein the predetermined number of word lines per block is reduced by a factor n (n is whole number greater than 1) while the number of the blocks is increased to n times, thereby reducing the number of word lines crossing a bit line by a factor n.